Senior Silicon Digital RTL Design Engineer
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- 5 years of experience with Intellectual Property (IP) Development or Integration.
Preferred qualifications:
- Experience with low power design techniques such as multiple power domains, clock gating, or dynamic voltage/frequency scaling.
- Experience with Analog or Mixed Signal designs.
- Experience working with highly scaled CMOS processes, such as FinFET.
- Experience with design-for-test (DFT) flows and methodology.
- Experience in one or more scripting languages (e.g., Python, TCL, etc.).
- knowledge of version control systems such as Git.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
You will architect, design, and verify digital logic using Verilog and SystemVerilog, standard checks such as Clock Domain Crossing (CDC) and lint, and digital simulation/DV techniques. You will interface with physical design teams (from synthesis through PnR and signoff) to ensure efficient, low power and timing-clean physical implementation of digital logic designs, constraining designs and reviewing Static Timing Analysis (STA) reports. You will engage with cross-functional teams to integrate digital logic with system-on-a-chip subsystems such as compute cores, communication interfaces, and analog/mixed-signal IP. You will work with production and silicon validation teams to support chip bring-up and production test.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Architect, design and verify digital logic using Verilog and SystemVerilog.
- Interface with physical designers to generate high quality physical implementations through synthesis, place-and-route, timing closure and verification.
- Engage with system architects and sub-system owners to define specifications and chip functions.
- Perform power, area and performance trade-off analyses of digital designs and architectures.
- Apply engineering best practices (e.g. code review, testing, refactoring) to the design and implementation of ASIC blocks.
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