Board Design Engineer
- linkCopy link
- emailEmail a friend
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 2 years of experience in high-speed board design (schematic and layout supervision) for server, networking, or high-performance computing products.
- Experience designing with high-speed serial interfaces (e.g., SerDes, PCIe, Ethernet, DDR) and signal integrity (insertion loss, crosstalk, impedance matching).
- Experience with DC-DC power converter design and power integrity concepts.
- Experience bringing up SoCs and debugging interaction between hardware, firmware, and software.
Preferred qualifications:
- Proficiency with EDA tools (e.g., Cadence Concept/Allegro, or similar).
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Lead the schematic capture and component selection for high-density, multi-layer PCBs (20+ layers) incorporating high-power ASICs (TPUs/CPUs), FPGAs, and high-speed memory (HBM/DDR5).
- Design and validate high-speed interfaces including PCIe Gen 6.0/7.0, 400G/800G/1.6T Ethernet (PAM4). Collaborate with Signal Integrity (SI) engineers to define routing constraints and stack-up.
- Design multi-phase power regulators (VRMs) capable of delivering >1000A currents with fast transient response for AI processors.
- Work with PCB layout designers to guide placement and routing of critical signals and power planes.
- Lead the lab bring-up of first-silicon/first-board by debugging hardware issues using oscilloscopes, TDRs, and logic analyzers to root-cause failures to component, assembly, or design issues.
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy.
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.