Signal Integrity Engineer, Google Platforms
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Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
- 2 years of experience working on system-level signal integrity design, or 1 year of experience with an advanced degree.
- Experience with component-level and integrated system testing and high speed digital interconnect design.
- Experience with SI/PI design techniques, including printed circuit board routing rules.
Preferred qualifications:
- Master's degree or PhD degree in Materials Science, Electrical Engineering, Computer Engineering, Physics, or a related field.
- Experience with lab measurements and analysis, including Oscilloscopes, Vector Network Analyzer (VNA), or TDR.
- Experience in scripting for data collection and analysis (Python, Bash), with strong data analysis skills and excellent attention to detail.
- Experience with Allegro, ADS, and Matlab.
- Knowledge of Printed Circuit Board (PCB), connector, or cable design and assembly processes, including materials and component selection.
- Familiarity with Ethernet, PCIE, DDR standards, and 56Gbps PAM4.
About the job
The team will design and build the hardware, software and networking technologies that power all of Google's services.
As a Signal Integrity and Power Integrity Engineer, you will design and build the systems that form the foundation of computing infrastructure. You will work on everything from low-level circuit design to large system design, overseeing these systems through to manufacturing. You will help shape the machinery powering data centers, impacting millions of Google users.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Collaborate with board, package, and chip design engineers to drive system SI design, explore SI/PI, layout and Design for Manufacturability (DFM) trade-offs, and ensure that product functions as required.
- Work with executive engineers to drive ASIC, package, board, connector, and cable vendors to develop next Generation interconnect technologies.
- Perform system interconnect bring-up and qualification (in collaboration with test engineers), including chip configuration to ensure adequate margins.
- Drive solutions for SI/PI issues with design engineers, PCB designers, and system team.
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