Chip Packaging Technologist
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with package development for high volume production.
- 8 years of experience with advance packaging technology development
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience working within assembly houses (OSATs) or wafer foundries.
- Knowledge of general package assembly processes, material selection, and reliability requirements at both the component and board levels.
- Understanding of the interactions between packaging technology, electrical design, thermal/mechanical performance, and manufacturability.
- Proficiency in 2.5D and 3D packaging technologies and advanced substrates for High-Performance Computing (HPC) applications.
- Proven track record in developing new technologies, driving innovation, and successfully implementing advanced packaging solutions.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Be part of a team developing custom silicon solutions for Google's direct-to-consumer products. Your expertise will shape next-generation hardware experiences, delivering unparalleled performance and integration. We are seeking an experienced packaging engineer with strong leadership and project management skills who is detail-oriented and operationally focused.
In this role, you will work with multi-disciplinary teams throughout custom silicon development, focusing on package substrate technology, design tradeoffs, assembly process evaluation, and mechanical reliability. As a Chip Packaging Technologist, you will develop advanced packaging solutions (2.5D/3D/3.5D) for ML chips. This involves collaborating with architects, Signal Integrity/Power Integrity (SI/PI), Thermal, and Printed Circuit Board (PCB) engineers to create high-performance packages optimized for electrical performance and assembly. You will be instrumental in identifying and incorporating advanced technologies into Google’s product design. You will be building the systems at the core of the computing infrastructure. You will see systems from fundamental circuit design through to high-volume manufacturing, directly impacting many of the Google users worldwide.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Define feasible boundaries for chip construction with architecture teams and own the packaging product lifecycle from initial definition through New Product Introduction (NPI).
- Drive packaging solutions (2.5D/3D) from concept to production, integrating manufacturing, electrical, thermal, and mechanical requirements.
- Develop and qualify advanced substrate solutions and build the ecosystem and supply chain necessary to support next-generation package architectures.
- Drive collaboration with internal teams, Outsourced Assembly and Test (OSATs), and suppliers to deliver production-ready solutions that maintain strict quality and reliability standards.
- Define Design for Excellence (DFx) methodologies and establish engineering plans using test vehicles to mitigate technical risks and ensure assembly process reliability.
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