Staff Physical Design Engineer
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In-office locations: Sunnyvale, CA, USA.
Remote location(s): Florida, USA.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience managing third-party vendor engagements and technical delivery schedules in an ASIC design environment.
- Experience in design synthesis, Logic Equivalence Checking (LEC) (e.g., Formality or Conformal), and Static Timing Analysis (STA).
- Demonstrated ability to debug technical issues within the RTL-to-netlist flow and collateral handoff processes.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in low power design implementation including UPF/CPF and multi-voltage domains.
- Experience with scripting languages such as Tcl or Python to automate and improve design workflows.
- Familiarity with hierarchical Place and Route (PNR) construction, timing closure, and relevant design rules in modern process nodes.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
The Google Cloud TPU team is responsible for designing and delivering the custom silicon that powers Google's AI/ML infrastructure. Our physical design team transforms RTL into large-scale, high-performance ASICs. This role serves as a technical authority for physical design execution, establishing a holistic methodology that ensures both schedule predictability and a competitive final product across our portfolio of reticle-scale designs.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $192,000-$278,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Lead and manage technical engagements with third-party vendors, overseeing project workstreams and schedules to ensure timely execution.
- Manage the handoff of design collateral to external partners, performing quality checks to ensure data integrity and methodology alignment.
- Drive design synthesis and Logic Equivalence Checking (LEC) using industry-standard tools such as Formality or Conformal.
- Perform basic Static Timing Analysis (STA) and debug issues arising in synthesis, LEC, etc.
- Oversee internal teams performing targeted physical design work on select blocks to ensure success before vendor-side signoff and artwork release.
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