Silicon Security Test and Verification Engineer
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 2 years of experience in SOC/IP DV.
- Experience with verification methodology such as SV and UVM.
- Experience in ARM security architecture.
Preferred qualifications:
- Familiarity with SoC level DV/UVM environment.
- Knowledge of JTAG/APB/AHB/AXI based protocols.
- HDL (Verilog/VHDL), HVL (System Verilog, OVM, ARM-C), and SVA (System Verilog Assertions) and experience with simulators and debug tools (VCS, NCVerilog, Novas)
- Knowledge of ATE pattern generation/conversion, Virtual Tester simulation, and Bench CSV generation.
- Ability to write scripts in Perl, Python or bash.
About the job
Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Collaborate with internal design teams to define requirements and support Silicon OTP fusing, repair, and provisioning flows.
- Simulate and debug at RTL/Gate level/Timing, ATE/Bench pattern generation with target coverage and Silicon Debug in close collaboration with SoC Development teams.
- Work independently with simulators and debug tools including VCS, NCVerilog, and Novas.
- Understand SoC level DV/UVM environment and JTAG/APB/AHB/AXI based protocols and the requirements for verifying SubSystems.
- Deliver automation flows using scripting languages such as Python, Perl, Skill, and TCL and demonstrate knowledge of ATE pattern generation/conversion, Virtual Tester simulation, and Bench CSV generation.
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