Technical Lead, ASIC IP and Subsystem Design, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience in ASIC design.
- Experience in RTL development with Verilog/SystemVerilog.
Preferred qualifications:
- Master's degree or PhD in Materials Science, Electrical Engineering, Computer Engineering, Physics, or a related field.
- Experience in high-performance design, multi power domains with complex clocking and multiple SoCs with silicon success.
- Experience with micro architecture design.
- Knowledge of system design to develop highly optimized IPs with excellent PPA.
- Understanding of computer architecture including industry standard interfaces and memory subsystems.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Work on a team of RTL engineers with IP/Subsystem development: plan tasks, hold code and design reviews, code development of complex features in the IP/Subsystem.
- Interact with the architecture team and develop implementation (microarchitecture and coding) strategies to meet quality, schedule, and Performance, Power, Area (PPA) for the IP.
- Work with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.
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