SoC Power and Performance Lead, TPU, Google Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in development of complex ASICs.
- 8 years of experience in architecture, micro-architecture, and design of ASICs/SoCs.
- Experience defining and driving power management and power delivery strategies.
- Experience in power modeling and driving low power implementations.
Preferred qualifications:
- Experience with performance modeling tools.
- Knowledge of accelerator architectures and data center workloads.
- Knowledge of high performance and low power design techniques.
About the job
In this role, you will be part of a team developing next generation AI accelerators for data centers. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation. Power and Performance are key focus areas for data centers, and you will play a vital role in shaping the future of data centers.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Lead all aspects of power definition and implementation for AI/ML SoCs.
- Collaborate with the architecture team on power-performance trade-off analysis as part of product definition.
- Drive power management and power delivery schemes, power rail definitions, and implementation strategies working closely with platform and package teams.
- Model power envelopes at various workloads and performance points.
- Drive power estimation, modeling, power roll ups, and pre silicon and post silicon correlation.
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