Silicon Reliability Engineer, Raxium
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Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, Physics, a related field, or equivalent practical experience.
- 4 years of experience in semiconductor IC reliability, or 3 years of experience with an advanced degree.
- 3 years of experience with reliability and qualification of semiconductor devices.
Preferred qualifications:
- Master's or PhD degree in Electrical Engineering, Physics, or a related field.
- 8 years of experience in display driver IC or semiconductor IC reliability.
- Experience in building or designing reliability hardware and driving failure analysis for reliability failures.
- Knowledge of reliability standards and experience with driving and implementing DFR methodology including Failure Mode and Effects Analysis (FMEA).
- Strong knowledge of semiconductor device performance requirements and test methodology, particularly for CMOS IC or display backplane products.
- Excellent database and programming skills, including data extraction, analysis, and visualization with commonly used tools like JMP, Reliasoft, etc.
About the job
As a Silicon Reliability Engineer, you will be responsible for developing and continuously improving reliability for the backplane in microLED-based displays. You will take the lead in developing the necessary hardware, executing reliability tests, performing in-depth analysis, and providing product reliability predictions. Collaboration with cross-functional teams will be essential to ensure outstanding reliability performance in our next-generation display products.
Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.
The US base salary range for this full-time position is $147,000-$216,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Own and execute various reliability and readpoint tests, data analysis/reporting, and manage stress schedules for the microLED backplane silicon.
- Work with Design-for-Test (DFT) and test development teams to ensure all design for reliability features are baked into the stress test patterns.
- Work with PCB design and test development teams to bring-up burn-in hardware for backplane (CMOS) ICs.
- Work with external vendors to design custom IC packaging and hardware for ESD and latch-up testing.
- Lead failure analysis and root cause discussions with relevant teams. Provide reliability input at the product design reviews meetings to ensure product reliability requirements are met.
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