ASIC Design Verification Engineer, Google Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 3 years of experience in verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
- Experienced with the full verification life-cycle.
- Experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog for Application-Specific Integrated Circuits (ASICs).
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.Responsibilities
- Plan the verification of digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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