Power and Performance Architect, TPU
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 15 years of experience in the design or definition of computer chips (such as SOC, CPU, GPU, or hardware accelerators).
- Experience with performance analysis or performance modeling.
- Experience with power analysis, power modeling, or power delivery systems.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience taking silicon power features from architecture definition through to tape-out and post-silicon validation.
- Experience with machine learning (ML) accelerator architecture and workload characterization for power optimization.
- Experience implementing DVFS or AVS, multi-voltage domain designs, and cross-layer power policies.
- Knowledge of system software components (Linux kernel, drivers) and their impact on runtime power/thermal behavior.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.As a Power and Performance Architect, you will be a technical lead responsible for defining and driving the power architecture roadmap for Google’s next-generation TPU SOCs. You will focuses on bridging the gap between high-level architectural concepts and silicon execution, ensuring that sophisticated power management features are successfully implemented to meet demands.In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Power and Performance Architect, you will be a technical lead responsible for defining and driving the power architecture roadmap for Google’s next-generation TPU SOCs. You will focuses on bridging the gap between high-level architectural concepts and silicon execution, ensuring that sophisticated power management features are successfully implemented to meet demands.
The US base salary range for this full-time position is $240,000-$334,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Responsibilities
- Lead the definition of power architecture for the next generation of TPU SOCs, optimizing for performance-per-watt across machine learning (ML) workloads.
- Bridge the architecture-to-execution gap by partnering with SOC implementation, IP providers, and hardware and software validation teams.
- Drive the design and integration of power management features, including dynamic voltage and frequency scaling (DVFS), power gating, and thermal mitigation strategies.
- Collaborate with the software community and data center teams to provide technology roadmaps that align silicon capabilities with system-level power constraints.
- Provide technical leadership and mentorship across multidisciplinary teams to anticipate future data center architectures and define SOC requirements.
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