SoC Microarchitect, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience in the microarchitecture of domains such as Graphics Processing Unit (GPU), Neural Processing Unit (NPU), Artificial intelligence (AI) Accelerators, low-power Digital Signal Processors (DSPs), or high-speed memory controllers (Low Power Double Data Rate (LPDDR).
- Experience with low-power design techniques and power management architectures (e.g., UPF/CPF, multi-voltage/power domains).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in managing full-chip functional constraints for synthesis and static timing analysis.
- Knowledge of CDC/RDC verification methodologies.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As an SoC Microarchitect, you will be a key technical leader responsible for defining and driving the detailed microarchitecture of high-performance, low-power System-on-Chips (SoCs) and their constituent Intellectual Property (IP) blocks. Your work will directly impact the Power, Performance, and Area (PPA) goals of Google's custom silicon, ensuring our products deliver exceptional efficiency and user experiences.
Responsibilities
- Define, develop, and document the microarchitecture specifications for complex SoC subsystems (e.g., interconnect, memory, media, AI/ML accelerators) and key IP blocks to meet ambitious functional, performance, power, and area requirements.
- Own the definition and microarchitecture of critical SoC-wide global infrastructure, including clocking, reset, power management, debug infrastructure (Design for Debug (DFD)/Design for Excellence (DFX), and top-level interconnects.
- Define and drive design methodologies for integration, with a specific focus on Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) design and verification, and lead functional constraints management across the SoC.
- Evaluate architectural trade-offs, identify bottlenecks, and validate microarchitectural decisions against product use cases and engaged benchmarks.
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