Silicon Senior Design Verification Engineer, TPU, Google Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 5 years of experience with verification methodology such as UVM/OVM/VMM.
- 3 years of experience in the verification of IP designs such as CPU, Peripherals, PMU, etc.
- Experience with SystemVerilog, SVA and functional coverage.
Preferred qualifications:
- Master's degree in Electrical Engineering or a related field.
- 10 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.
- Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
- Experience creating and using verification components and environments in standard verification methodology.
- Experience with ASIC standard interfaces and memory system architecture.
- Experience in verification of AI/ML Accelerators.
About the job
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools. Develop cross-language tools and scalable verification methodologies.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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