FPGA Design Verification Engineer, Quantum AI
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience verifying digital systems using SystemVerilog/UVM.
- 5 years of experience inSOC Verification including CPUs, bus interfaces, or peripherals.
- 5 years of experience using scripting languages (such as Python or Perl) for automation and analysis.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or Computer Science.
- 8 years of experience in design verification.
- Experience running DV for mixed-signal ASICs containing analog and RF IP and building mixed-mode models for end-to-end DV coverage.
- Experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, or 360-DV.
- Experience in ARM, RISC-V or any processor based DV including tool chains and C based testing.
- Knowledge of verification strategy definition, verification planning, coverage closure and UVM environment setup.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be a vital member of the quantum electronics team, providing key technical contributions in the area of field programmable gate array (FPGA) and, potentially, ASIC design verification (DV) as we realize sophisticated electronics for control and readout of our future quantum computers. You will work as part of a team of digital, DV, physical design (PD), and request for (RF)/analog/mixed-signal engineers, collaborating with adjacent teams in the electronic, software, and quantum engineering areas to implement FPGA-based systems for use in the readout and control of our scaled quantum processors. You will help drive the DV of all of Quantum’s control and readout electronics. You will contribute to the verification of our FPGAs, collaborating with architects and digital designers to understand the chip functional requirements, plan out verification plans, and drive execution of those plans in collaboration with other DV engineers. You will build out and track coverage metrics to ensure robust and thorough verification of designs. You will also work with external IP vendors, overseeing the DV work that they directly provide on their own IP and collaborating with these vendors to create suitable DV integration coverage.
The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Build and maintain hardware-in-the-loop testing platforms while integrating any verification IP for externally developed IP into our overall verification flow.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
- Create and execute verification plans and test cases. Identify and debug verification failures.
- Develop and maintain constrained-random verification environments using System Verilog and universal verification methodology (UVM).
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
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