Security Design Verification Engineer, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 5 years of industry experience, such as verifying RTL using Systemverilog and UVM.
- Experience verifying IP or digital systems incorporating standard IP components and interconnects.
Preferred qualifications:
- Master's degree in Electrical Engineering or Computer Science.
- Experience creating and using verification components and environments in a standard verification methodology.
- Experience with constrained-random verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
- Experience with GLS, Power-aware DV, and support of SOC DV.
- Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture.
About the job
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan the verification of complex security IPs and Subsystem by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using System Verilog and UVM.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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