SoC RTL Design Engineer, TPU
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development.
- Experience with digital clock control circuits, including clock dividers, glitch-free muxes, and clock gating.
- Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL.
- Experience with design quality tools, specifically for Clock Domain Crossing (CDC), linting, and static timing analysis.
- Experience using Python, Tcl, or Perl for automating design tasks and data analysis.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of experience with high-performance ASIC design in PLL, FLL, and DLL integration.
- Experience implementing clock skipping, Dynamic Voltage and Frequency Scaling (DVFS), and fine-grained clock gating for low-power SoC optimization.
- Proficiency in Python or Perl for automating design scripts and analyzing complex clock-tree data.
- Understanding of clock distribution challenges, including jitter, skew management, and duty-cycle distortion.
- Ability to lead cross-functional efforts from initial specification through silicon bring-up.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Join the team designing and developing the core components of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers.
As a Clock Control Unit (CCU) Design Engineer, you will be the architect of the SoC, owning the logic that generates and distributes clocks across the entire silicon fabric. This is a high-impact role where you will independently design complex clocking infrastructures—including FLL (Frequency-Locked Loops)/PLL (Phase-Locked Loops) controllers and advanced clock-skipping mechanisms, to balance extreme performance with power management. You will serve as the primary technical lead for the CCU, partnering with architecture, power, and physical design teams to ensure a glitch-free, timing-closed clocking network. Your work will directly enable the power-efficiency and operational stability of our next-generation accelerators from initial microarchitecture through to silicon bring-up.
This position offers the opportunity to handle challenging technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Define specifications and develop SystemVerilog for advanced clocking features, including FLL/PLL controllers, dividers, and glitch-free multiplexer logic.
- Design and optimize dynamic power-saving mechanisms such as clock skipping (pulse swallowing), frequency scaling sequences, and fine-grained clock gating.
- Partner with architecture teams to evaluate clock-tree impacts and implement infrastructure supporting various SoC power states and performance levels.
- Collaborate with Physical Design teams to manage skew, jitter, and multi-cycle paths, ensuring the CCU meets stringent timing and area goals.
- Work with Design Verification and Silicon bring-up teams to create test plans for clocking corner cases and root-cause issues in simulation and emulation.
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