Silicon AI/ML Design Verification Lead, TPU
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 8 years of experience with verification methodology such as UVM.
- 8 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
- 4 years of experience in people management, developing employees.
- Experience with SystemVerilog, SVA and functional coverage.
Preferred qualifications:
- Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
- Experience scripting using Python, Perl, or shell scripts.
- Experience leading and managing complex verification projects.
- Understanding of ARM instruction set architecture.
About the job
Own the full verification life cycle: from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy targets. Build robust, constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of AI/ML workloads on TPU hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.
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Responsibilities
- Develop and execute verification plans. Architect, develop, and maintain verification test benches that support both random and directed testing.
- Participate in design, architecture, and code reviews. Work closely with micro architects, architects and design teams, and influence design decisions/feature intercepts.
- Lead performance validation for both pre-silicon and post-silicon. Work with emulation/FPGA prototyping teams in verifying system level use cases.
- Drive convergence of verification and coverage plans towards high quality and on-time tape-out. Drive methodology initiatives to improve efficiency and design quality.
- Lead a team of design verification engineers focusing on IP, Subsystem/SoC verification at unit, cluster, subsystem, and full chip levels.
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