Infrastructure Tools and Methodology Lead
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
- 6 years of experience in people management, developing employees.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience planning and deploying new tools and flows to users.
- Knowledge of chip design process, either verification, design or implementation.
- Ability to present and explain novel methods to users.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.As a Technical Lead within Google's hardware team, you will help deliver products that have an impact on the Technical Infrastructure that powers Google. You will provide leadership to a group of hardware engineers in an innovative and fluid environment with a focus on infrastructure for chip design. You will also lead complex technical projects from the concept/planning stage through execution and closure. In this role, you will help your team deliver designs that work first time in a number of different application areas. You will be leveraging your technical and leadership expertise. You will also lead chip design process improvement projects in multiple areas of expertise.
Responsibilities
- Lead chip methodology engineers to provide support for chip teams, and also manage and mitigate support issues for tool flows.
- Partner with chip project teams to influence and standardize methodology across functional areas (Design, DV, PD).
- Perform or guide technical evaluations of tools for possible deployment.
- Collaborate with teams across Google to identify and create strategic opportunities for improved chip design across Google.
- Participate in design reviews and track issue resolution and engage in technical and schedule trade-off discussions.
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