Memory Layout Design Engineer
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Minimum qualifications:
- Bachelor’s degree in VLSI/Computer Engineering or equivalent practical experience.
- 2 years of experience designing and drawing layout of high-speed/low power memories.
- Experience with developing memory array layout (Row decoders, Write drivers, Assist circuits, Sense Amplifiers, Memory Control circuit) in 3nm (or equivalent) technology node.
- Experience with integrating various blocks of memory array and integrating memory array at SoC level.
Preferred qualifications:
- Master's degree in VLSI/Computer Engineering, or a related field.
- Experience drawing layout for Sense Amplifier, Decoders, Assist Circuits, Latches, Flip-Flops, Isolation Cells, Power Switches, and Level Shifters.
- Experience with placement, track planning, and integration of various blocks within SRAM memories.
- Experience with Virtuoso XL and extraction tools such as Star-RC/QFS.
- Understanding of layout design rules, layout dependent effects, and DFM in FinFET technology nodes.
About the job
The Google Foundation IP Enablement team is looking for a Memory Layout Design Engineer to augment Power, Performance, and Area (PPA) of Digital Circuit IP’s used in Google Silicon products.
In this role, you will engage with Architects, Physical Designers, Silicon Design Engineers, Test-Chip team, and External Foundry teams to improve PPA of Google Silicon. You will also have the opportunity to collaborate with the post-silicon team to debug silicon issues and correlate silicon-spice results.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Integrate various blocks of memory array and optimize leaf cell layout used in memory arrays to achieve best PPA.
- Track planning and power grid planning of memory arrays.
- Run LVS/DRC/density checks and fix EM/IR violations.
- Work with the circuit design team to improve PPA of memory array or std-cell.
- Collaborate with the physical design team to ensure that GDS can be integrated within the SoC.
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