Senior SoC DFT Engineer, Google Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, or equivalent practical experience.
- 8 years of experience in DFT infrastructures (e.g., structural verification, automation).
- Experience with DFT industry Electronic Design Automation (EDA) tools.
- Experience with Joint Test Action Group (JTAG) standards (e.g., IEEE 1149, 1687).
- Experience with DFT/physical design mutual aspects and dependencies.
- Experience in Automatic Test Pattern Generation (ATPG) from strategy through assimilation to production and analytics.
Preferred qualifications:
- Master's degree in Electrical Engineering, or a related field.
- Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST).
- Experience in SoC cycles, silicon bring-up, and silicon debug activities.
- Experience working with Automatic Test Equipment (ATE) Engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues).
- Experience working with post silicon groups, debug, and analytics.
- Experience in fault modeling.
About the job
As an Executive SoC Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation System-on-a-chip (SoC). You will design, insert, and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers. In addition, you will also be responsible for reducing test cost, increasing production quality, and enhancing yield.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Define and develop DFT architecture, design, and verification. Develop DFT strategy for large-scale ASICs, including hierarchical DFT.
- Work with chip architecture, IP design, physical design, and post silicon groups. Develop flows and methodologies to support production of large-scale
Application-Specific Integrated Circuit (ASIC). - Implement DFT logic components and Register-Transfer Level (RTL) coding of DFT bridges. Work with both Electronic Design Automation (EDA) and internally developed DFT tools.
- Define DFT requirements for third-party IP’s and implement DFT supporting logic. Develop DFT flows, methodologies, and automation.
- Mentor and provide technical leadership for other DFT engineers.
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