ASIC RTL Design Lead, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
- Experience with a scripting language like Perl or Python.
- Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities
- Define the microarchitecture for Intellectual Property (IP) blocks, subsystems, and Systems-on-Chip (SoCs), collaborating with cross-functional teams to deliver high-quality designs that meet strict schedules and optimized Power, Performance, and Area (PPA).
- Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.
- Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform RTL coding for Subsystem (SS) and System-on-Chip (SoC) integration, function/performance simulation debug, Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and Unified Power Format (UPF) checks.
- Ability to utilize key design collaterals, specifically Synopsys Design Constraints (SDC) and Unified Power Format (UPF), while collaborating with stakeholders to disscuss quality standards and develop technical workarounds for integration issues.
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