RTL Design Engineer, Google Cloud, University Graduate, 2025 Start
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Minimum qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, a related technical field, or equivalent practical experience.
- Experience with SystemVerilog or other scripting languages (e.g., python, perl, assembly, bash, etc.).
Preferred qualifications:
- Master's degree in Electrical Engineering or a related field.
- Experience with one or more of the following: Micro Architecture, Design, Verification, Logic Synthesis, Timing Closure, Assertion-based Formal Verification.
- Ability to learn quickly and be proactive and motivated.
- Excellent sense of ownership, commitment and responsibility.
- Strong communication skills.
About the job
As a RTL Design Engineer, you will join our team and gain experience across the entire ASIC design lifecycle. You will collaborate closely with architecture, design, and verification engineers, developing Register-Transfer Level (RTL) code and executing block-level simulations. You will also address technical challenges by crafting innovative micro-architecture and practical logic solutions, and you will evaluate design tradeoffs considering performance, power, and area optimization.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Own a complex ASIC subsystem.
- Define high-performance micro architecture and design specifications.
- Collaborate closely with Architecture, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
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