Power Integrity Engineer, Platforms Engineering
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Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
- 2 years of experience working in a system-level power delivery network design, analysis, and validation technical environment, or 1 year of experience with an advanced degree.
- Experience with power management methodologies, power delivery, and signal integrity interactions of common I/O interfaces.
- Experience with PCB, package and silicon technologies, and their impact on power delivery solutions.
Preferred qualifications:
- Master's or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field.
- Experience in power integrity fundamentals, including board power conversion design for motherboard, data center hardware products, and power integrity conversion design.
- Experience with lab measurement, validation and correlation at package, Die, and PCB level.
- Experience with Electronic design automation tools.
- Knowledge of system power delivery networks and switching voltage regulator modeling and simulation.
- Knowledge of 3D/2D electromagnetic simulation tools, lab equipment, and scripting languages.
About the job
As a Hardware Engineer, you design and build the systems that are the heart of the computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into data centers affecting users.With your technical expertise, you will lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation, troubleshooting, and debugging with vendors.
As a Power Integrity Engineer, you will play a key role in the development of computing infrastructures. You will work as part of a team to deliver innovative power solutions for point of load application. You will design, analyze, optimize, and implement board, substrate package, and chip level power delivery topologies for point of load application including Application-Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and processors.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Innovate and design on board, on substrate and on chip level Power Delivery Networks (PDN). Analyze performance, cost, reliability and availability design trade-offs.
- Provide technical leadership and direction while troubleshooting complex system level power delivery issues.
- Work cross-functionally with Project teams, on system bring up and design validation.
- Perform lab design validation, correlation study, and root cause debugging.
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