Circuit Design Engineer, Devices and Services, Silicon
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Minimum qualifications:
- Bachelor’s degree in VLSI, Computer Engineering, or Electronics Engineering, or equivalent practical experience.
- 5 years of experience designing Register File Memory Arrays
- Experience with HSPICE or equivalent circuit simulator, and writing SPICE decks.
- Experience with shell scripting (e.g. sed/awk).
Preferred qualifications:
- Master's degree in VLSI, Computer Engineering, or Electronics Engineering.
- Experience designing digital circuits like Adders, Level Shifters, Multipliers, Retention Flops, and Register File Memory Design.
- Experience with writing SPICE decks, running SPICE simulations, and performing high-sigma variation analysis.
- Understanding of CMOS Transistor Short Channel and Layout Dependent Effects in FinFET and GAA technology.
- Proficiency in Python, Perl, TCL, or shell scripts
About the job
In this role, you will augment PPA of Digital Circuit IPs used in Google Silicon products. You'll engage with Architects, Physical Designers, Silicon Design Engineers, the Test-Chip team, and External Foundry teams to improve PPA of Google Silicon. You will collaborate with the post-silicon team to debug silicon issues and correlate Silicon-SPICE results.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Analyze design specifications from Compute IP's and develop custom memory arrays or std-cells.
- Draw Schematics, Extract Layout, Write Spice Deck and Run Spice simulations to validate the circuit (or block).
- Run Monte-Carlo OR High-Speed sigma analysis to understand sensitivity of designed circuit.
- Work with Layout engineer to improve PPA of memory array or std-cell.
- Collaborate with Physical Design team and ensure seamless integration of std-cell or memory array.
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