Senior Staff Chip Package Signal Integrity Engineer
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience working cross functionally with chip top design, physical design, short text analysis (STA), package, system, validation teams.
- Experience in high speed serdes IP evaluation , post silicon validation, and debugging.
- Experience with 2.5D/3D package design such as silicon interposer, silicon bridge, 3D die stacking.
- Knowledge of channel design and sign off as well as serdes system modeling (e.g., BER, SNR, etc.) for speeds beyond 112Gbps.
- Knowledge of next generation serdes (e.g., 200G/400G ethernet, PCIeG6/7) and package technology.
About the job
In this role, you will design and build the hardware, software, and networking technologies that power all of Google's services. You will design and build the systems computing infrastructure. You will see from concept to manufacturing to shape the machinery that goes into data centers.
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The US base salary range for this full-time position is $221,000-$314,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Responsibilities
- Lead the design of chips, packages, and systems for high speed serdes interface by analyzing end-to-end Signal integrity and Power Integrity (SIPI) to ensure optimal performance in 2.5D/3D package technology for High Performance Computing (HPC) and working with cross-functional teams to define SI/PI design goals, boundaries, and trade-offs for chip/package design closure
- Establish and drive our roadmap of high speed serdes including Analog Front End (AFE) and Digital Signal Processor (DSP) requirements.
- Validate post-silicon and qualification for new product introduction (NPI).
- Evaluate and integrate high-speed SerDes IPs.
- Participate in IEEE P802.3dj working group.
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